SerDes Validation Leader

SerDes Validation Lead

Who we are

We are a startup building foundational technology to address performance, scalability, and resiliency challenges in large-scale AI data center clusters. We are backed by top-tier VC firms and notable angel investors.

The company is led by experienced builders and operators who have founded companies, taken them to scale, and exited successfully. We work with a strong sense of unity and shared responsibility, and we expect trust, integrity, and respect in how we collaborate and make decisions. We hold ourselves accountable to one another and to the quality of the work we deliver.

Headquartered in Silicon Valley, we operate across a mix of remote and on-site locations in the U.S. and Canada. We aim to create an environment where people are treated fairly, supported in their growth, and empowered to do meaningful work alongside others who take the craft seriously.

About the role

We are seeking a SerDes Implementation Lead to own the physical-layer implementation, configuration, tuning, and post-silicon validation of ultra-high-speed data links, including 112G and 224G PAM4.

This is a hands-on technical role for someone who has taken SerDes IP macros from integration through bring-up, tuned equalization parameters in real systems, and driven links to stable operation across challenging physical channels. You will work closely with signal integrity, power integrity, hardware, and firmware teams to correlate real-world channel behavior with transceiver settings and system-level performance.

What you’ll do

• Drive implementation and register-level configuration of high-speed SerDes IP blocks across custom hardware systems.

• Own transceiver equalization tuning, including CTLE, FFE, and DFE tap optimization, to maximize eye margin and minimize bit error rates across cable, backplane, and board-level topologies.

• Lead post-silicon physical-layer bring-up, characterization, and debugging of 112G and 224G PAM4 links.

• Use high-bandwidth oscilloscopes, BERTs, pattern generators, and protocol analyzers to validate link performance and isolate issues.

• Collaborate closely with SI/PI engineers to correlate lab-measured link behavior with layout, simulation, and channel models.

• Work with firmware teams to support real-time link monitoring, configuration control, and automated validation flows.

• Develop and run script-based lab automation, including Python-based test, measurement, and characterization workflows.

• Help define best practices for SerDes bring-up, tuning, debug, and validation across the company’s hardware platforms.

What we’re looking for

• Proven hands-on experience bringing up and validating physical 56G, 112G, or 224G PAM4 links, or high-speed PCIe Gen5/Gen6 interfaces.

• Deep practical understanding of SerDes implementation, configuration, equalization, and physical-layer debug.

• Strong knowledge of how TX/RX equalization settings affect signal integrity, jitter profiles, eye margin, and BER.

• Advanced proficiency with high-speed lab equipment, including BERTs, real-time or sampling oscilloscopes, pattern generators, and protocol analyzers.

• Experience with automated, script-based testing and lab characterization, preferably using Python.

• Ability to debug complex link issues across silicon, board, cable, backplane, firmware, and system-level interactions.

• Strong collaboration skills and the ability to work closely with SI/PI, hardware, firmware, and systems teams in a fast-moving engineering environment.

Nice to have

• Experience with 112G or 224G PAM4 links in data center, networking, switch, accelerator, or high-performance compute environments.

• Familiarity with Ethernet, PCIe, CXL, or other high-speed protocols.

• Experience working with SerDes IP from major commercial IP providers or custom in-house SerDes teams.

• Exposure to channel modeling, compliance testing, and production validation flows.

Compensation:

Target ba